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#ifndef _PLATF_INFO_H_
#define _PLATF_INFO_H_

// IPU version & Platform versions
typedef enum _IPU_VERSION
{
    IPU_Unk,
    IPU_4,
    IPU_4P,
    IPU_5,
    IPU_6,
    IPU_6SE,
    IPU_6EP,
    IPU_7,
    IPU_75XA,
    IPU_8
} IPU_VER;

typedef enum _PLATFORM_VERSION
{
    PLT_Unk,
    PLT_APL,
    PLT_BXTHR,
    PLT_CNL_Bx,
    PLT_CNL_C0,
    PLT_CNL_D0,
    PLT_ICL,
    PLT_ICL_C0,
    PLT_ICL_D0,
    PLT_LKF_Ax,
    PLT_LKF_Bx,
    PLT_TGL_A0,
    PLT_TGL_Bx,
    PLT_TGL_H_A0,
    PLT_JSL,
    PLT_ADL,
    PLT_ADL_N,
    PLT_RPL,
    PLT_MTL,
    PLT_ARL,
    PLT_LNL_A,
    PLT_LNL,
    PLT_PTL,
    PLT_PTL_H_A,
    PLT_PTL_U,
    PLT_NVL,
    PLT_NVL_S
} PLT_VER;

typedef enum _HARDWARE_TYPE
{
    HW_SILICON,
    HW_FPGA,
    HW_SIMICS
} HW_TYPE;

typedef struct
{
    IPU_VER        ipuVer;
    PLT_VER        pltVer;
    HW_TYPE        hwType;
    long           phyLaneMask;
    long           phySpeedMask;
    unsigned long  WindowsBuildNumber;
    char           brandName[0x40];
} PLAT_INFO, *PPLAT_INFO;

#define is_slim_ipu(plt_ver) (    \
    plt_ver == PLT_TGL_H_A0    || \
    plt_ver == PLT_JSL            \
)

#define is_lkf_ipu(plt_ver) (       \
    plt_ver == PLT_LKF_Ax       || \
    plt_ver == PLT_LKF_Bx           \
)

#define is_full_ipu(plt_ver) (    \
    ((plt_ver >= PLT_TGL_A0) && (plt_ver < PLT_TGL_H_A0)) ||    \
    plt_ver == PLT_ADL          || \
    plt_ver == PLT_MTL            \
)

#define is_adl_ipu(plt_ver)  ((plt_ver >= PLT_ADL) && (plt_ver < PLT_MTL))
#define is_mtl_ipu(plt_ver)  ((plt_ver >= PLT_MTL) && (plt_ver < PLT_ARL))
#define is_lnl_ipu(plt_ver)  (plt_ver == PLT_LNL || plt_ver == PLT_LNL_A)
#define is_ptl_ipu(plt_ver)  ((plt_ver >= PLT_PTL) && (plt_ver < PLT_NVL))
#define is_nvl_ipu(plt_ver)  (plt_ver == PLT_NVL || plt_ver == PLT_NVL_S)

#endif
